The present invention relates generally to digital signal processors (DSPS) and, more particularly, to data communications between one DSP and other DSPs.
Advances in very large scale integration have contributed to the current digital signal processors (DSPs). These processors are special purpose microprocessors characterized by architectures and instructions suitable for digital signal processing applications. DSPs are utilized in a number of applications from communications and controls to speech and image processing. Special purpose DSPs, designed for a specific signal processing application such as for fast fourier transform (FFT) have also emerged.
One such DSP, for example the TMS320C30, supports fixed- and floating-point operations. Features of this processor include 32 bit by 32 bit floating-point multiply operations in one instruction cycle time of 60 nsec. Since a number of instructions, such as load and store, multiply and add, can be performed in parallel in one cycle time, the TMS320C30 can execute a pair of instructions in 30 nsec, allowing for 33.3 MIPS. The TMS320C30 has 2K words of on-chip memory and 16 million words of addressable memory spaces for program, data and input/output. Specialized instructions are available to make common DSP algorithms, such as filtering and spectral analysis, execute fast and efficiently. Like other microprocessors, the DSP may take advantage of higher level languages, such as C and ADA.
In a system having multiple independent DSPs, it is often necessary to send data from one DSP to another DSP, and for one DSP to inform or signal another DSP that the data is ready. Also, after the DSP has read the data provided from the other DSP, it must signal the other DSP that the data has been read. This ensures that new data is not provided prior to the DSP having had an opportunity to read the old data.
A conventional method of exchanging data between a source DSP and a destination DSP involves using a shared external or internal memory that each DSP may access to pass the data. An interrupt signal or flag is also provided to signal the destination DSP that the data is available. A conventional system for exchanging data between two DSPs is shown in FIG. 1. Conventional system 10 includes DSPxcfx86 and DSP1, respectively designated 13 and 14, sharing local memory 12. Other devices 11 also share local memory 12. Each device, for example DSPxcfx86, writes to or reads data from local memory 12 by way of its data bus, and by placing the address of local memory 12 on its address bus. A write/read command determines whether the data is sent to the local memory from DSPxcfx86 or data is received from the local memory by DSPxcfx86.
In operation, the source DSP, for example DSPxcfx86, desires to send data to the destination DSP, for example DSP1. Before the data is sent, source DSPxcfx86 reads a flag from FLAGxcfx86 (designated 15) located in shared memory 12 to ensure that it is not overwriting a previous data word placed in location DATAxcfx86 (designated 16). If the previous data word has already been read, DSPxcfx86 writes the data to DATAxcfx86 and writes a new flag value to FLAGxcfx86. DSPxcfx86 then signals DSP1, by way of an interrupt (for example interrupt signal 17). The interrupt informs DSP1 that the data is available. Next in sequence, DSP1 reads the data from the shared memory and writes a new flag value to FLAGxcfx86.
Disadvantages associated with system 10 include large latency periods incurred when accessing an external, shared resource. If other devices are also permitted to access the shared resource, bandwidth of the shared resource is reduced. Exchanging data through a shared memory requires additional code, the code tending to become complex. Additional operations tie up the shared resource and prevent other devices from using the resource.
A need exists, therefore, to provide a system for exchanging data between processors that does not require use of a shared resource or memory.
To meet this and other needs, and in view of its purposes, the present invention provides an apparatus and method for exchanging data between two independent processors. In a multiple processor environment that has first and second processors, the invention includes a first message unit and a second message unit. The first message unit is coupled between the first processor and the second message unit, and the second message unit is coupled to the second processor. The first message unit stores first data from the first processor and transfers the stored first data to the second message unit. The second message unit stores the first data from the first message unit and responsively provides the first data to the second processor. The second message unit also stores second data from the second processor and transfers the stored second data to the first message unit, and the first message unit stores the second data from the second message unit and responsively provides the second data to the first processor.
The first message unit also provides a first interrupt signal to the second processor for informing the second processor that the first data is available for reading, and the second message unit provides a second interrupt signal to the first processor for informing the first processor that the second data is available for reading. In addition, the first message unit provides a first flag signal for informing the first processor that the second processor has read the first data, and the second message unit provides a second flag signal for informing the second processor that the first processor has read the second data.
It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.